One way of decreasing power consumption is to use lower supply voltage and this method is now often used for the new generations of microprocessors. Non-isolated voltage regulation modules (VRM) or isolated DC-DC converters must deliver now much more current and must sustain very high current transients. Telecom standard bricks are facing the same challenge too. As illustrated schematically in FIG. 11, paralleling more DC-DC converters 10 for current sharing to achieve high current capability and better power distribution is a preferred approach to supply low voltage high current power to power bus lines 12. This has become a standard solution for many applications. Besides current sharing and current transient control, one paralleling DC-DC converters has to take into consideration the start-up sequence and the impact of each converter's soft-start on the main power bus. The start-up sequence of the converter can be controlled, more or less, at the system level; but the soft-start behaviour is an internal matter of each converter and must be dealt with at this level.
Powering up in non-zero output condition has become an important issue for paralleled converters in power bus systems. Regular switching power supplies need to have a soft monotonic start up and they are using synchronous rectification in order to reach high efficiency. When paralleling more synchronous rectification converters into power bus systems, the problem of current sharing and start up sequence control can be handled at system level, but the internal soft start of converters is in conflict with the powered bus and this problem must be dealt with at each converter level.
The capability of synchronous rectification converters to process power bi-directionally becomes a drawback when the internal regulation point of the converter does not coincide with its output level. Typically, a converter's output voltage follows a reference voltage. When the output level on the bus is already higher than the one set by the reference of the converter, the energy starts to flow backwards, from the output to the input of the converter. In transient situations, as the soft start of converter, there is nothing to limit the backwards surge of power; the power bus is perturbed by it and the converter itself can be damaged or even destroyed.
Prior art methods operate by controlling the way in which synchronous rectifiers become active or the moment when they are enabled. The practical solutions are many times complex and the results are limited. Some power bus systems have an independent switch to connect each converter only after the soft start is finished; the cost is affected and the system efficiency too, especially for low voltage and high current power buses.
The Typical Soft Start
A regular converter needs an internal soft-start control in order to eliminate the transient behavior at turn-on. FIG. 1 illustrates turn-on without soft start control. Here, a 3.3V unit is protected only by its current limit feature. Channel 1 represents the output voltage (2V/div) and Channel 2 represents the output current (20 A/div). The evident over-shoots and oscillations need to be eliminated. An increasing monotonic shape of output voltage has to be achieved.
As illustrated in FIG. 2, the logarithmic shape given by a RC circuit is one of the most popular solutions for the internal soft starting reference of converters. For obtaining a soft-start the majority of designs assure a soft rise of a reference 20 that controls the voltage loop, forcing the output 21 to follow it. Charging a capacitor through a resistor offers a nice shape and the control loop will follow this shape.
One can see that, using this logic, the voltage loop reference 20 is the master and the output 21 is the slave, as shown in FIG. 2. The voltage control loop is forcing the output 21 to follow the reference 20 and the soft start shape of the output 21 is obtained. For the majority of today's converters the soft-start control presumes a close to zero output voltage at turn-on T0, as shown in FIG. 2.
This condition is not fulfilled when a pre-bias 25 is presented on the output as illustrated in FIG. 5 and the initial output voltage on the power bus must be taken into consideration. The pre-bias 25 is present when the DC-DC converter is connected to a powered bus where it powers up. Within the converter the reference 20/output 21 relationship has a master/slave characteristic and the converter will force the output 21 to come close to the reference 20 level no matter what. The pre-bias 25 condition of the output 21 conflicts with the transient regulation point of the converter, resulting in a back flow of the energy and a drop 26 of the initial output voltage. The initial difference results in a discharging of the output capacitors and recharging them back as the reference 20 rises. It is a clear waste of energy. When the pre-biased output is sustained by a power bus, the output voltage cannot drop and the conflict is even stronger.
As mentioned, all synchronous rectifier converters have the capability to process power in both directions and this can be an advantage or a disadvantage over normal rectifier converters. Synchronous rectifier converters have higher overall efficiency and they can easily work with light or no load. Of course, the synchronous rectifiers are more complex and more expensive, but the present increase in demand of low voltage and high current power supplies have made them the best solution in computers, data and telecommunication fields.
When a synchronous rectifier converter has on its output a higher voltage than the one its voltage loop is trying to regulate the result will consist in a backward power flow—from the output to the input. This power flow is a disadvantage especially when this energy is taken from a powered bus, in fact from other converters that sustain this bus. The overall efficiency will decrease dramatically and the stability of the entire system can be jeopardized. Normally a current sharing circuitry is managing the steady-state running of the power bus, forcing all the converters to match the bus voltage. Yet some errors still appear.
The turn-on behavior of each converter is normally out of the current sharing control. Because the individual soft-start does not take in consideration the real level of output voltage —the bus voltage—an important difference is appearing between the voltage loop target—starting from zero—and the output voltage. A huge instantaneous backward power flow can appear in this situation and, beside the inconvenience of loosing useful power and over—stress the power bus, this can be dangerous for the converter itself. The current limit protection of the converters is normally unidirectional and it cannot control the current flowing back. Some power buses have an active switch for each converter output in order to prevent such conflicts, but this solution is costly and decreases the total efficiency of the system.
A practical solution consists in disabling the synchronous rectifiers of the converter at the beginning of a turn-on sequence, so the power flow is forced internally to be unidirectional. Even so, a new problem is generated when the synchronous rectifiers are activated because a perturbation will be generated into the voltage loop control. This affects directly the normal soft-start shape of the converter. The moment when the synchronous rectifiers are enabled is also important. For a voltage mode controlled converter (VMC) the variation between a body diode voltage drop and a low voltage drop across a power MOSFET will produce a change in the loop condition and its gain. The proportion of output perturbation depends on voltage loop speed and the percentage relationship of synchronous rectifier body diode drop to the output. The direction of this perturbation depends on load condition; a discontinuous current of the output inductor prior to synchronous rectifier activation will generate an output voltage drop, pushing energy backward, and a continuous current of the output inductor prior to activation will generate an output voltage boost. A feed-forward compensation can help to minimize this perturbation, eliminating the impact of “on time”, but the “off time” of the switching period will still be influenced by the synchronous activation.
A current mode control (CCM) can help in minimizing the output perturbation, but this kind of control is not always easy to implement and may not be cost acceptable. Some other drawbacks can appear, as slow response for output current transients.
A second solution is used to solve the back flow problem, consisting in a “soft activation” of the synchronous rectifiers. This method controls the voltage applied on MOSFET gates, trying to modulate the channel conductivity. The translation between disable and fully enable must be soft enough for the voltage loop to keep control of the output. Some improvement can be achieved using this solution, but there are limitations.
First, today's power MOSFET gain around the turn-on threshold is too big for a good linear modulation of channel conductivity. Second, the channel resistance to begin with is too small for its modulation to have an important effect. The performances of a 1.8V/30 A Telecom eight brick, available on today market and featuring a “soft activation” control, are next analyzed.
The level of flowing back current when the unit starts in a pre-bias voltage of 80% of its own nominal output was chosen as a first analysis criteria. A 30,000 μF capacitance was used to force the pre-bias voltage on converter. FIG. 3 presents the results. Channel 1 represents the output voltage (1V/div) of the converter and Channel 2 represents its output current (20 A/div).
For more than 500 μs the converter is pushing back current and the initial peak is reaching a negative level of −23 A. The negative current is limited by the “softness” of the synchronous rectifiers. FIG. 4 shows the same unit starting-up in a 100% pre-biased output voltage, which represents the second analysis criteria. The push back time extends to almost 1 ms and the negative peak current reaches −54 A, far more than the normal maximum current. Such a high current is unacceptable in normal running and is for sure very dangerous when it flows in the opposite direction.
The voltage perturbation of the capacitive bus is obvious and its drop also helps in limiting the negative current. For a real powered bus the voltage drop will be minimized, but the level of negative current will be higher. There is a big chance for the negative power flow to exceed the maximum tolerable level of the converter.
Many pulse width modulation (PWM) ICs have a fully integrated soft-start control and many others have a soft-start behavior controlled by several external components. The first kind minimizes the cost but reduces the flexibility. The second offers more flexibility, but increases the cost. Sometimes designers choose a complete independent soft-start circuitry in order to achieve better performances and maximum of flexibility at the expense of price.
In all these cases the voltage soft-start has to assure an increasing monotonic shape for the output, from zero to the nominal voltage. The over-shoots and oscillations must be eliminated, and if the output current does exceed the maximum value, the current limit protection must take over the control. Charging big output capacitors is a challenge that today's converters must meet. The logarithmic shape given by a RC circuit is one of the most popular solutions. Linear shape or multiple slopes shapes are also used. New digital controllers can also provide solutions. However when converters turn on into a powered bus a “classic” voltage soft-start circuitry is unable to control the flow of power.